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Intel(R) CoreTM2 Duo Processor and Intel(R) CoreTM2 Extreme Processor on 45-nm Process for Platforms Based on Mobile Intel(R) 965 Express Chipset Family
Datasheet
January 2008
Document Number: 318914-001
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Datasheet
Contents
1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 8 1.2 References ......................................................................................................... 9 Low Power Features ................................................................................................ 11 2.1 Clock Control and Low-Power States .................................................................... 11 2.1.1 Core Low-Power State Descriptions........................................................... 13 2.1.2 Package Low-Power State Descriptions...................................................... 15 2.2 Enhanced Intel SpeedStep(R) Technology .............................................................. 19 2.3 Extended Low-Power States................................................................................ 20 2.4 FSB Low-Power Enhancements............................................................................ 21 2.4.1 Dynamic FSB Frequency Switching ........................................................... 21 2.4.2 Intel(R) Dynamic Acceleration Technology ................................................... 22 2.5 VID-x .............................................................................................................. 22 2.6 Processor Power Status Indicator (PSI-2) Signal .................................................... 22 Electrical Specifications ........................................................................................... 23 3.1 Power and Ground Pins ...................................................................................... 23 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................... 23 3.3 Voltage Identification ......................................................................................... 23 3.4 Catastrophic Thermal Protection .......................................................................... 26 3.5 Reserved and Unused Pins.................................................................................. 27 3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 27 3.7 FSB Signal Groups............................................................................................. 27 3.8 CMOS Signals ................................................................................................... 29 3.9 Maximum Ratings.............................................................................................. 29 3.10 Processor DC Specifications ................................................................................ 30 Package Mechanical Specifications and Pin Information .......................................... 37 4.1 Package Mechanical Specifications ....................................................................... 37 4.2 Processor Pinout and Pin List .............................................................................. 46 Thermal Specifications ............................................................................................ 71 5.1 Thermal Features .............................................................................................. 73 5.1.1 Thermal Diode ....................................................................................... 73 5.1.2 Intel(R) Thermal Monitor........................................................................... 74 5.1.3 Digital Thermal Sensor............................................................................ 76 5.2 Out of Specification Detection ............................................................................. 77 5.3 PROCHOT# Signal Pin ........................................................................................ 77
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Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Core Low-Power States .............................................................................................12 Package Low-Power States ........................................................................................13 C6 Entry Sequence ...................................................................................................18 C6 Exit Sequence .....................................................................................................18 Active VCC and ICC Loadline Standard Voltage and Extreme Edition Processors ................33 Deeper Sleep VCC and ICC Loadline Standard Voltage and Extreme Edition Processors ......34 6-MB and 3-MB on 6-MB Die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ........38 6-MB and 3-MB on 6-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ........39 6-MB and 3-MB on 6-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)........40 6-MB and 3-MB on 6-MB die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ........41 3-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ........................................42 3-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ........................................43 3-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ........................................44 3-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ........................................45 Processor Pinout (Top Package View, Left Side) ............................................................46 Processor Pinout (Top Package View, Right Side) ..........................................................47
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Coordination of Core Low-Power States at the Package Level..........................................13 Voltage Identification Definition ..................................................................................23 BSEL[2:0] Encoding for BCLK Frequency......................................................................27 FSB Pin Groups ........................................................................................................28 Processor Absolute Maximum Ratings..........................................................................29 Voltage and Current Specifications for the Extreme Edition Processors .............................30 Voltage and Current Specifications for the Dual-Core Standard Voltage Processors ............32 FSB Differential BCLK Specifications ............................................................................34 AGTL+ Signal Group DC Specifications ........................................................................35 CMOS Signal Group DC Specifications..........................................................................36 Open Drain Signal Group DC Specifications ..................................................................36 Pin Listing by Pin Name .............................................................................................48 Pin Listing by Pin Number ..........................................................................................55 Signal Description.....................................................................................................62 Power Specifications for the Extreme Edition Processor ..................................................71 Power Specifications for Dual-Core Standard Voltage Processors .....................................72 Thermal Diode Interface ............................................................................................73 Thermal Diode Parameters using Transistor Model ........................................................74
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Revision History
Document Number 318914 Revision Number -001 Initial release Description Date January 2008
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Introduction
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Introduction
The Intel(R) CoreTM2 Duo processor and Intel(R) CoreTM2 Extreme processor built on 45nanometer process technology are the next generation high-performance, low-power mobile processors based on the Intel(R) CoreTM microarchitecture. The Intel Core 2 Duo processor and Intel Core 2 Extreme processor support the Mobile Intel(R) 965 Express Chipset and Intel(R) 82801HBM ICH8 Controller Hub-Based Systems. The document contains electrical, mechanical and thermal specifications for the following processors: * Intel Core 2 Duo processor - Standard Voltage * Intel Core 2 Extreme processor
Note:
In this document, the Intel Core 2 Duo processor and Intel Core 2 Extreme mobile processor built on 45-nm process technology are referred to as the processor. The Mobile Intel(R) 965 Express Chipset family is referred to as the (G)MCH. The following list provides some of the key features on this processor: * Dual-core processor for mobile with enhanced performance. * Supports Intel(R) architecture with Intel(R) Wide Dynamic Execution. * Supports L1 cache-to-cache (C2C) transfer. * Supports PSI2 functionality. * Supports Enhanced Intel(R) Virtualization Technology. * On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each core. * On-die, up to 6-MB second-level shared cache with Advanced Transfer Cache Architecture. * Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), Supplemental Streaming SIMD Extensions 3 (SSSE3) and SSE4.1 Instruction Sets. * 800-MHz Source-Synchronous front side bus (FSB). * Advanced power management features including Enhanced Intel SpeedStep(R) Technology and Dynamic FSB frequency switching. * Digital Thermal Sensor (DTS). * Intel(R) 64 architecture. * Intel(R) Dynamic Acceleration Technology and Enhanced Multi-Threaded Thermal Management (EMTTM). * Micro-FCPGA and Micro-FCBGA packaging technologies (Extreme Edition only available in Micro-FCPGA). * Execute Disable Bit support for enhanced security. * Deep Power-Down Technology with P_LVL6 I/O Support. * Half-ratio support (N/2) for Core-to-Bus ratio.
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Introduction
1.1
Terminology
Term Definition A "#" symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the "#" symbol implies that the signal is inverted. For example, D[3:0] = "HLHL" refers to a hex `A', and D[3:0]# = "LHLH" also refers to a hex "A" (H= High logic level, L= Low logic level). Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel(R) processors. Technology that provides power management capabilities to laptops. The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel(R) Architecture Software Developer's Manual for more detailed information. Refers to the interface between the processor and system core logic (also known as the chipset components). Penryn processor support the N/2 feature which allows having fractional core to bus ratios. This feature provides the flexibility of having more frequency options and be able to have products with smaller frequency steps. 64-bit memory extensions to the IA-32 architecture. Processor virtualization which, when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core. Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air" (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Thermal Design Power. The processor core power supply. The processor ground.
#
AGTL+ Enhanced Intel SpeedStep(R) Technology
Execute Disable Bit
Front Side Bus (FSB) Half ratio support (N/2) for Core to Bus ratio Intel(R) 64 Technology Intel(R) Virtualization Technology Processor Core
Storage Conditions
TDP VCC VSS
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Introduction
1.2
References
Document Intel(R) CoreTM2 Duo Mobile Processor and Intel(R) CoreTM2 Extreme Processor on 45-nm Technology Specification Update Mobile Intel(R) 965 Express Chipset Family Datasheet Mobile Intel(R) 965 Express Chipset Family Specification Update Intel(R) I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Datasheet Intel(R) I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Specification Update Document Number 318915 316273 316274 See http://www.intel.com/ design/chipsets/datashts/ 313056.htm See http://www.intel.com/ design/chipsets/specupdt/ 313057.htm See http://www.intel.com/ design/pentium4/manuals/ index_new.htm See http:// developer.intel.com/design/ processor/specupdt/ 252046.htm 253665 253666 253667 253668 253669
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Intel(R) 64 and IA-32 Architectures Software Developer's Manuals Documentation Change Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide
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Introduction
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Datasheet
Low Power Features
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2.1
Low Power Features
Clock Control and Low-Power States
The processor supports low-power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel(R) Enhanced Deeper Sleep, and Intel Deep Power-Down low-power states. When both cores coincide in a common core low-power state, the central power management logic ensures the entire processor enters the respective package low-power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, P_LVL5,P_LVL6) I/O read to the (G)MCH. The processor implements two software interfaces for requesting low-power states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor's I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does not need to be set up before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the IA32_MISC_ENABLES modelspecific register (MSR). If a core encounters a chipset break event while STPCLK# is asserted, it then asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to the system logic that individual cores should return to the C0 state and the processor should return to the Normal state. Figure 1 shows the core low-power states and Figure 2 shows the package low-power states for the processor. Table 1 maps the core low-power states to package low-power states.
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Low Power Features
Figure 1.
Core Low-Power States
Stop Grant
STPCLK# asserted STPCLK# de-asserted STPCLK# de-asserted STPCLK# STPCLK# asserted de-asserted STPCLK# asserted HLT instruction
C1/ MWAIT
Core state break
C1/Auto Halt
MWAIT(C1)
Halt break
C0
Core State break P_LVL4 or
o P_LVL5/P_LVL6 MWAIT(C4/C6)
P_LVL2 or MWAIT(C2) Core state break
C2
C4
/C6
P_LVL3 or Core MWAIT(C3) state break
C3
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) -- STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. -- Core C4 state supports the package level Intel Enhanced Deeper Sleep state. O -- P_LVL5/P_LVL6 read is issued once the L2 cache is reduced to zero.
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Low Power Features
Figure 2.
Package Low-Power States
STPCLK# asserted SLP# asserted DPSLP# asserted DPRSTP# asserted
Normal
STPCLK# de-asserted
Stop Grant
SLP# de-asserted
Sleep
DPSLP# de-asserted
Deep Sleep
DPRSTP# de-asserted
Deeper Sleep
Snoop serviced
Snoop occurs
Stop Grant Snoop
-- Deeper Sleep includes the Deeper Sleep state, Intel Enhanced Deeper Sleep state, and C6 state
Table 1.
Coordination of Core Low-Power States at the Package Level
Core 1 State C0 Normal Normal Normal Normal Normal C1 Normal Normal Normal Normal Normal C2 Normal Normal Stop-Grant Stop-Grant Stop-Grant C3 Normal Normal Stop-Grant Deep Sleep Deep Sleep C4/C6 Normal Normal Stop-Grant Deep Sleep Deeper Sleep/Intel(R) Enhanced Deeper Sleep/ Intel(R) Deep Power-Down
Package State Core 0 State C0 C11 C2 C3 C4/C6
NOTES: 1. AutoHALT or MWAIT/C1.
2.1.1
2.1.1.1
Core Low-Power State Descriptions
Core C0 State
This is the normal operating state for cores in the processor.
2.1.1.2
Core C1/AutoHALT Power-Down State
C1/AutoHALT is a low-power state entered when a core executes the HALT instruction. The processor core will transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT power-down state. See the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.
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Low Power Features
While in AutoHALT power-down state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT powerdown state.
2.1.1.3
Core C1/MWAIT Power-Down State
C1/MWAIT is a low-power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.
2.1.1.4
Core C2 State
Individual cores of the dual-core processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in the C2 state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the C2 state.
2.1.1.5
Core C3 State
Individual cores of the dual-core processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor's L2 cache. Except for the caches, the processor core maintains all its architecture in the C3 state. The monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core's caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual-core processor accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.
2.1.1.6
Core C4 State
Individual cores of the dual-core processor can enter the C4 state by initiating a P_LVL4 or P_LVL5 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, the central power management logic will request that the entire processor enter the Deeper Sleep package low-power state (see Section 2.1.2.6). To enable the package-level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the PMG_CST_CONFIG_CONTROL MSR. Refer to Section 2.1.2.6 for further details on Intel Enhanced Deeper Sleep state.
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Low Power Features
2.1.1.7
Core C6 State
C6 is a radical, new, power-saving state which is being implemented on this processor. In C6 the processor saves its entire architectural state onto an on-die SRAM, hence allowing it to run at a voltage VC6 that is lower than Enhanced Deeper Sleep voltage. An individual core of the dual-core processor can enter the C6 state by initiating a P_LVL6 I/O read to the P_BLK or an MWAIT(C6) instruction. The primary method to enter C6 used by newer operating systems (that support MWAIT) will be through the MWAIT instruction. When the core enters C6, it saves the processor state that is relevant to the processor context in an on-die SRAM that resides on a separate power plane VCCP (I/O power supply). This allows the main core VCC to be lowered to a very low-voltage VC6. The ondie storage for saving the processor state is implemented as a per-core SRAM. The microcode performs the save and restore of the processor state on entry and exit from C6, respectively.
2.1.2
2.1.2.1
Package Low-Power State Descriptions
Normal State
This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted, each core of the dual-core processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low-power state. When the STPCLK# pin is deasserted, each core returns to its previous core low-power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC Specification T45. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted after the deassertion of SLP#, as per AC Specification T75. While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in the Stop-Grant state. PBE# will be asserted if there is any pending interrupt or Monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state. A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) occurs with the assertion of the SLP# signal.
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Low Power Features
2.1.2.3
Stop-Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.
2.1.2.4
Sleep State
The Sleep state is a low-power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.2.5
Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset-based platforms are as follows: * Deep Sleep entry: the system clock chip may stop/tristate BCLK within two BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep. * Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in the Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in the Deep Sleep state. When the processor is in the Deep Sleep state it will not respond to interrupts or snoop transactions.
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Low Power Features
Warning:
Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior.
2.1.2.6
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels. One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is achieved by entering the Intel Enhanced Deeper Sleep state, which is a sub-state of the Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.3 for further details on reducing the L2 cache and entering the Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins. Refer to the platform design guides for further details. Exit from Deeper Sleep or the Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point.
2.1.2.6.1
Intel(R) Enhanced Deeper Sleep State Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters the Intel Enhanced Deeper Sleep state: * The last core entering C4 issues a P_LVL4 or P_LVL5 I/O read or an MWAIT(C4) instruction and then progressively reduces the L2 cache to zero. * Once the L2 cache has been reduced to zero, the processor triggers a special chipset sequence to notify the chipset to redirect all FSB traffic, except APIC messages, to memory. The snoops are replied as misses by the chipset and are directed to main memory instead of the L2 cache. This allows for higher residency of the processor's Intel Enhanced Deeper Sleep state. * The processor drives the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins.
2.1.2.6.2
Intel(R) Deep Power-Down State (Previously known as Package C6 State) When both cores have entered the CC6 state and the L2 cache has been shrunk down to zero ways, the processor will enter the Intel Deep Power-Down state or C6 state. To do so both cores save their architectural states in the on-die SRAM that resides in the VCCP domain. At this point, the core VCC will be dropped to the lowest core voltage VC6. The processor is now in an extremely low-power state. In the Intel Deep Power-Down state, the processor does not need to be snooped, as all the caches are flushed before entering C6. C6 exit is triggered by the chipset when it detects a break event. It deasserts the DPRSTP#, DPSLP#, SLP#, and STPCLK# pins to exit the processor out of the C6 state. At DPSLP# deassertion, the core VCC ramps up to the LFM value and the processor starts up its internal PLLs. At SLP# deassertion the processor is reset and the architectural state is read back into the cores from an on-die SRAM. The restore will be done in both cores irrespective of the break event and which core it is directed to. The C6 exit event will put both cores in CC0. Refer to Figure 3 and Figure 4 for C6 entry sequence and exit sequence.
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Figure 3.
C6 Entry Sequence
Core1
CC0 mwait C6 or Level 6 I/O Read State Save CC6
Level 6 I/O Read
stpclk assert
slp assert
dpslp assert
dprstp assert
Package C6
Core0
CC0 mwait C6 or Level 6 I/O Read L2 Shrink State Save CC6
Figure 4.
C6 Exit Sequence
Core 0
CC0
State Restore Package C6 dpsl deassert
ucode reset
dprst deassert
H/W Reset
sl deassert
stpclk deassert ucode reset
State Restore
CC0
Core 1
2.1.2.6.3 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: * The second core is already in C4 and Intel Enhanced Deeper Sleep state or C6 state is enabled (as specified in Section 2.1.1.6). * The C0 timer that tracks continuous residency in the Normal package state has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed. * The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed-to-processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing decisions.
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Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep state or C6 will expand the L2 cache to two ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters the Intel Enhanced Deeper Sleep state or C6, then the L2 will be shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then the whole L2 will be expanded upon the next interrupt event. In addition, the processor supports Full Shrink on L2 cache. When the MWAIT C6 instruction is executed with a hint=0x2 in ECX[3:0], the micro code will shrink all the active ways of the L2 cache in one step. This ensures that the package enters C6 immediately when both cores are in CC6 instead of iterating till the cache is reduced to zero. The operating system (OS) is expected to use this hint when it wants to enter the lowest power state and can tolerate the longer entry latency. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not enter Intel Enhanced Deeper Sleep state or C6 since the L2 cache remains valid and in full size.
2.2
Enhanced Intel SpeedStep(R) Technology
The processor features Enhanced Intel SpeedStep Technology. The key features of Enhanced Intel SpeedStep Technology follow: * Multiple voltage and frequency operating points provide optimal performance at the lowest power. * Voltage and frequency selection is software controlled by writing to processor MSRs: -- If the target frequency is higher than the current frequency, VCC is ramped up in steps by placing new values on the VID pins, and the PLL then locks to the new frequency. -- If the target frequency is lower than the current frequency, the PLL locks to the new frequency, and the VCC is changed through the VID pin mechanism. -- Software transitions are accepted at any time. If a previous transition is in progress the new transition is deferred until the previous transition completes. * The processor controls voltage ramp rates internally to ensure glitch-free transitions. * Low transition latency and large number of transitions possible per second: -- Processor core (including L2 cache) is unavailable for up to 10 s during the frequency transition. -- The bus protocol (BNR# mechanism) is used to block snooping.
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Low Power Features
* Improved Intel(R) Thermal Monitor mode: -- When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable MSR. -- The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up-transition to the previous frequency and voltage point occurs. -- An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system-level thermal management. * Enhanced thermal management features: -- Digital Thermal Sensor and Out of Specification detection -- Intel(R) Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in case of unsuccessful TM2 transition. -- Dual-core thermal management synchronization. Each core in the dual processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage. The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic Acceleration Technology mode on select SKUS. The operating system can take advantage of these features and request a lower operating point called SuperLFM (due to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic Acceleration Technology mode.
2.3
Extended Low-Power States
Extended low-power states (C1E, C2E, C3E, C4E, C6E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low-power state. Instead of directly transitioning into the package low-power state, the enhanced package low-power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low-power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in low-power states. C6 is always enabled in the extended low-power state, as described above.
Note:
Long-term reliability cannot be assured unless all the extended low power states are enabled. The processor implements two software interfaces for requesting extended package low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring IA32_MISC_ENABLES MSR bits to automatically promote package lowpower states to extended package low-power states.
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Extended Stop-Grant and Enhanced Deeper Sleep must be enabled via the BIOS for the processor to remain within specification. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor. As processor technology changes, enabling the extended low-power states becomes increasingly crucial when building computer systems. Maintaining the proper BIOS configuration is key to reliable, long-term system operation. Not complying to this guideline may affect the long-term reliability of the processor. Caution: Enhanced Intel SpeedStep Technology transitions are multi-step processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low-power states since processor clocks are not active in these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.
2.4
FSB Low-Power Enhancements
The processor incorporates FSB low-power enhancements: * Dynamic FSB Power-Down * BPRI# control for address and control input buffers * Dynamic Bus Parking * Dynamic On-Die Termination disabling * Low VCCP (I/O termination voltage) * Dynamic FSB frequency switching The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.
2.4.1
Dynamic FSB Frequency Switching
Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode (SuperLFM). This feature is supported at FSB frequencies of 800-MHz on the Santa Rosa platform and does not entail a change in the external bus signal (BCLK) frequency. Instead, both the processor and (G)MCH internally lower their BCLK reference frequency to 50% of the externally visible frequency. Both the processor and (G)MCH maintain a virtual BCLK signal ("VBCLK") that is aligned to the external BCLK,
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Low Power Features
but at half the frequency. After a downward shift, it would appear externally as if the bus is running with a 100-MHz base clock in all aspects except that the actual external BCLK remains at 200 MHz. The transition into Super LFM, a "down-shift," is done following a handshake between the processor and (G)MCH. A similar handshake is used to indicate an "up-shift," a change back to normal operating mode. Ensure this feature is enabled and supported in the BIOS.
2.4.2
Intel(R) Dynamic Acceleration Technology
The processor supports the Intel Dynamic Acceleration Technology mode. The Intel Dynamic Acceleration Technology feature allows one core of the processor to operate at a higher frequency point when the other core is inactive and the operating system requests increased performance. This higher frequency is called the "opportunistic frequency" and the maximum rated operating frequency is the "guaranteed frequency."
Note:
Extreme Edition processors do not support Intel Dynamic Acceleration Technology. Intel Dynamic Acceleration Technology mode enabling requires: * Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state * Enhanced Multi-Threaded Thermal Management (EMTTM) * Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via BIOS. When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be active under certain internal conditions. In such a scenario the processor may draw an Instantaneous current (ICC_CORE_INST) for a short duration of tINST; however, the average ICC current will be "lesser then" or "equal" to ICCDES current specification. Please refer to the Processor DC Specifications section for more details.
2.5
VID-x
The processor implements the VID-x feature for improved control of core voltage levels when the processor enters a reduced power consumption state. VID-x applies only when the processor is in the Intel Dynamic Acceleration Technology performance state and one or more cores are in low-power state (i.e., CC3/CC4/CC6). VID-x provides the ability for the processor to request core voltage level reductions greater than one VID tick. The amount of VID tick reduction is fixed and only occurs while the processor is in the Intel Dynamic Acceleration Technology mode. This improved voltage regulator efficiency, during periods of reduced power consumption, allows for leakage reduction that results in platform power savings and extended battery life.
2.6
Processor Power Status Indicator (PSI-2) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous mobile processors. For details, refer to the platform design guide for PSI-2. Functionality is expanded further to support three processor states when: * Both cores are in idle state. * Only one core is in active state. * Both cores are in active state.
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3
3.1
Electrical Specifications
Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Refer to the platform design guide for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
3.2
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous-generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor uses a differential clocking implementation.
3.3
Voltage Identification
The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 refers to a high-voltage level and a 0 refers to low-voltage level.
Table 2.
Voltage Identification Definition (Sheet 1 of 4)
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875
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Electrical Specifications
Table 2.
Voltage Identification Definition (Sheet 2 of 4)
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875
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Table 2.
Voltage Identification Definition (Sheet 3 of 4)
VID6 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875
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Electrical Specifications
Table 2.
Voltage Identification Definition (Sheet 4 of 4)
VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC (V) 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
3.4
Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted, and during package C6.
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3.5
Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6,TEST7 pins are used for test purposes internally and can be left as "No Connects".
3.6
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.
Table 3.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2] L L L L H H H H BSEL[1] L L H H H H L L BSEL[0] L H H L L H H L BCLK Frequency RESERVED RESERVED 166 MHz 200 MHz RESERVED RESERVED RESERVED RESERVED
3.7
FSB Signal Groups
The FSB signals have been combined into groups by buffer type in the following sections. AGTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous.
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Electrical Specifications
Table 4.
FSB Pin Groups
Signal Group AGTL+ Common Clock Input AGTL+ Common Clock I/O Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3, DPWR# Signals REQ[4:0]#, A[16:3]# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe A[35:17]# D[15:0]#, DINV0# D[31:16]#, DINV1# D[47:32]#, DINV2# D[63:48]#, DINV3# AGTL+ Strobes Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK Clock Associated Strobe ADSTB[0]# ADSTB[1]# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, IERR#, THERMTRIP# PROCHOT#4 PSI#, VID[6:0], BSEL[2:0] TCK, TDI, TMS, TRST# TDO BCLK[1:0] COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS, VSS_SENSE
CMOS Input Open Drain Output Open Drain I/O CMOS Output CMOS Input Open Drain Output FSB Clock Power/Other
NOTES: 1. Refer to Chapter 4 for signal descriptions and termination requirements. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no-connects. 3. BPM[2:1]# and PRDY# are AGTL+ output-only signals. 4. PROCHOT# signal type is open drain output and CMOS input. 5. On-die termination differs from other AGTL+ signals.
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3.8
CMOS Signals
CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups.
3.9
Maximum Ratings
Table 5 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded.
Caution:
Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. Processor Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinAsynch_CMOS Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS CMOS buffer DC input voltage with respect to VSS Min -40 -0.3 -0.1 -0.1 Max 85 1.45 1.45 1.45 Unit C V V V Notes1 2, 3, 4
Table 5.
NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be met. 2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long term reliability of the device. For functional operation, please refer to the processor case temperature specifications. 3. This rating applies to the processor and does not include any tray or packaging. 4. Failure to adhere to this specification can affect the long term reliability of the processor.
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Electrical Specifications
3.10
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Table 6 through Table 11 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the processor are at TJ = 105C. Read all notes associated with each parameter.
Table 6.
Symbol VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VDC4 VC6 ICCDES
Voltage and Current Specifications for the Extreme Edition Processors (Sheet 1 of 2)
Parameter VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) VCC at Super Low Frequency Mode (Super LFM) Default VCC Voltage for Initial Power-Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep VCC at Intel(R) Enhanced Deeper Sleep state VCC at Deep Power-Down Technology ICC for Processors Recommended Design Target ICC for Processors Processor Number X9000 Min 1.0 0.85 0.8 -- 1.000 1.425 0.65 0.60 0.35 -- -- -- -- -- -- 1.200 1.050 1.500 Typ Max 1.275 1.10 1.0 -- 1.100 1.575 0.85 0.85 0.70 59 -- -- 57 34 26 27.3 18.3 26.5 18.1 24.5 17.6 12.2 11.7 11.0 3, 4, 10, 12 3, 4, 10 3, 4, 10 3, 4, 10 3, 4 3, 4 3, 4 Unit V V V V V V V V V A 1, 2 1, 2 1, 2 Notes 1, 2 1, 2 1, 2 2, 5, 6, 7
Core Frequency/Voltage 2.8 GHz & VCCHFM 1.2 GHz & VCCLFM 0.8 GHz & VCCSLFM
ICC
--
--
A
IAH, ISGNT
ICC Auto-Halt & Stop-Grant HFM SuperLFM ICC Sleep HFM SuperLFM ICC Deep Sleep HFM SuperLFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep ICC Deep Power-Down Technology
--
--
A
ISLP
--
--
A
IDSLP IDPRSLP IDC4 IC6
-- -- -- --
-- -- -- --
A A A A
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Table 6.
Symbol dICC/DT ICCA ICCP
Voltage and Current Specifications for the Extreme Edition Processors (Sheet 2 of 2)
Parameter VCC Power Supply Current Slew Rate at Processor Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable Min -- -- -- Typ -- -- -- Max 600 130 4.5 2.5 Unit A/s mA A A 8 9 Notes 5, 9
NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 105C TJ. 4. Specified at the nominal VCC. 5. Measured at the bulk capacitors on the motherboard. 6. VCC,BOOT tolerance shown in Figure 5 and Figure 6. 7. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 8. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. 9. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high. 10. Processor ICC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM 11. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. 12. Intel Dynamic Acceleration Technology is not supported.
Datasheet
31
Electrical Specifications
Table 7.
Symbol VCCDAM VCCHFM VCCLFM VCCSLFM VCC,BOOT VCCP VCCA VCCDPRSLP VDC4 VC6 ICCDES
Voltage and Current Specifications for the Dual-Core Standard Voltage Processors
Parameter VCC in Intel Dynamic Acceleration Technology Mode VCC at Highest Frequency Mode (HFM) VCC at Lowest Frequency Mode (LFM) VCC at Super Low Frequency Mode (Super LFM) Default VCC Voltage for Initial Power-Up AGTL+ Termination Voltage PLL Supply Voltage VCC at Deeper Sleep VCC at Intel(R) Enhanced Deeper Sleep State VCC at Deep Power-Down Technology ICC for LV Processors Recommended Design Target ICC for Processors Processor Number Core Frequency/Voltage 2.6 2.5 2.4 2.1 1.2 0.8 GHz GHz GHz GHz GHz GHz & & & & & & VCCHFM VCCHFM VCCHFM VCCHFM VCCLFM VCCSLFM Min 1.000 1.000 0.850 0.750 -- 1.000 1.425 0.650 0.600 0.35 -- -- -- -- -- 1.200 1.050 1.500 -- -- -- -- -- -- Typ Max 1.300 1.250 1.025 0.95 -- 1.100 1.575 0.850 0.850 0.70 44 -- -- 44 44 44 44 28.6 22.4 23.3 13.7 22.7 13.5 21.0 13.0 11.7 10.5 5.7 600 130 4.5 2.5 Unit V V V V V V V V V V A 1, 2 1, 2 1, 2 13 Notes 1, 2 1, 2 1, 2 1, 2 2, 5, 7
ICC
T9500 T9300 T8300 T8100
--
--
A
3, 4, 11
IAH, ISGNT
ICC Auto-Halt & Stop-Grant HFM SuperLFM ICC Sleep HFM SuperLFM ICC Deep Sleep HFM SuperLFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep ICC Deep Power-Down Technology VCC Power Supply Current Slew Rate at Processor Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable
--
--
A
3, 4, 11
ISLP
--
--
A
3, 4, 11
IDSLP IDPRSLP IDC4 IC6 dICC/DT ICCA ICCP
-- -- -- -- -- -- --
-- -- -- -- -- -- --
A A A A A/s mA A A
3, 4, 11 3, 4 3, 4 3, 4 6, 8
9 10
NOTES:(Begin on next page.)
32
Datasheet
Electrical Specifications
1.
2.
3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. Specified at 105C TJ. Specified at the nominal VCC. Measured at the bulk capacitors on the motherboard. VCC,BOOT tolerance shown in Figure 5 and Figure 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low. This is a steady-state Icc current specification that is applicable when both VCCP and VCC_CORE are high. Processor ICC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. Instantaneous current ICC_CORE_INST of 55 A has to be sustained for short time (tINST) of 10 s. Average current will be less than maximum specified ICCDES. VR OCP threshold should be high enough to support current levels described herein.
Figure 5.
Active VCC and ICC Loadline Standard Voltage and Extreme Edition Processors
VCC-CORE [V]
Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required.
VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM}
10mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/
0
Note 1/ VCC-CORE Set Point Error Tolerance is per below : Tolerance --------------+/-1.5% +/-11.5mV VCC-CORE VID Voltage Range -------------------------------------------------------VCC-CORE > 0.7500V 0.5000 V ICC-CORE max {HFM|LFM}
ICC-CORE [A]
Datasheet
33
Electrical Specifications
Figure 6.
Deeper Sleep VCC and ICC Loadline Standard Voltage and Extreme Edition Processors
VCC-CORE [V]
Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required.
VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM}
13mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/
0
Note 1/ V C C - C O R E Set Point Error Tolerance is per below :
ICC-CORE max {HFM|LFM}
ICC-CORE [A]
Tolerance V C C - C O R E VID Voltage Range --------------- -------------------------------------------------------+/-[(VID*1.5%)-3mV] V C C - C O R E > 0.7500V +/-(11.5mV-3mV) Total tolerance window including ripple is +/-35mV for C6 0.5000V NOTE: Deeper Sleep mode tolerance depends on VID value.
Table 8.
FSB Differential BCLK Specifications
Symbol VCROSS VCROSS VSWING ILI Cpad Parameter Crossing Voltage Range of Crossing Points Differential Output Swing Input Leakage Current Pad Capacitance Min 0.3 -- 300 -5 0.95 Typ -- -- -- -- 1.2 Max 0.55 140 -- +5 1.45 Unit V mV mV A pF Notes1 2, 7, 8 2, 7, 5 6 3 4
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. For Vin between 0 V and VIH. 4. Cpad includes die capacitance only. No package parasitics are included. 5. VCROSS is defined as the total variation of all crossing voltages as defined in note 2. 6. Measurement taken from differential waveform. 7. Measurement taken from single-ended waveform. 8. Only applies to the differential rising edge (Clock rising and Clock# falling).
34
Datasheet
Electrical Specifications
Table 9.
AGTL+ Signal Group DC Specifications
Symbol VCCP GTLREF RCOMP RODT/A RODT/D RODT/Cntrl VIH VIL VOH RTT/A RTT/D RTT/Cntrl RON/A RON/D RON/Cntrl ILI Cpad Parameter I/O Voltage Reference Voltage Compensation Resistor Termination Resistor Address Termination Resistor Data Termination Resistor Control Input High Voltage Input Low Voltage Output High Voltage Termination Resistance Address Termination Resistance Data Termination Resistance Control Buffer On Resistance Address Buffer On Resistance Data Buffer On Resistance Control Input Leakage Current Pad Capacitance Min 1.00 0.65 27.23 48 48 48 0.82 -0.10 0.90 48 48 48 22 22 22 -- 1.80 Typ 1.05 0.70 27.5 55 55 55 1.05 0 VCCP 55 55 55 25 25 25 -- 2.30 Max 1.10 0.72 27.78 65 64 65 1.20 0.55 1.10 65 64 65 30 29.5 30 100 2.75 Unit V V V V V A pF 6 10 11, 12 11, 13 11, 14 3, 6 2, 4 6 7, 12 7, 13 7, 14 5, 12 5, 13 5, 14 8 9 Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull-down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured at 0.31*VCCP. RON (min) = 0.4*RTT, RON (typ) = 0.455*RTT, RON (max) = 0.51*RTT. RTT typical value of 55 is used for RON typ/min/max calculations. 6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. 7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics. 8. Specified with on die RTT and RON are turned off. Vin between 0 and VCCP. 9. Cpad includes die capacitance only. No package parasitics are included. 10. This is the external resistor on the comp pins. 11. On-die termination resistance, measured at 0.33*VCCP. 12. Applies to Signals A[35:3]. 13. Applies to Signals D[63:0]. 14. Applies to Signals BPRI#,DEFER#,PREQ#, RESET#, RS[2:0]#, TRDY#, ADS#, BNR#, BPM[3:0], BR0#, DBSY#, DRDY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#, ADSTB[1:0]#, DSTBP[3:0] and DSTBN[3:0]#.
Datasheet
35
Electrical Specifications
Table 10.
CMOS Signal Group DC Specifications
Symbol VCCP VIH VIL VOH VOL IOH IOL ILI Cpad1 Cpad2 Parameter I/O Voltage Input High Voltage Input Low Voltage CMOS Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current Pad Capacitance Pad Capacitance for CMOS Input Min 1.00 0.7 * VCCP -0.10 0.9 * VCCP -0.10 1.5 1.5 -- 1.80 0.95 Typ 1.05 VCCP 0.00 VCCP 0 -- -- -- 2.30 1.2 Max 1.10 VCCP+0.1 0.3 * VCCP VCCP+0.1 0.1 * VCCP 4.1 4.1 100 2.75 1.45 Unit V V V V V mA mA A pF pF 2 2, 3 2 2 5 4 6 7 8 Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Refer to the processor I/O Buffer Models for I/V characteristics. 4. Measured at 0.1*VCCP. 5. Measured at 0.9*VCCP. 6. For Vin between 0 V and VCCP. Measured when the driver is tristated.z 7. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are included. 8. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.
Table 11.
Open Drain Signal Group DC Specifications
Symbol VOH VOL IOL ILO Cpad Parameter Output High Voltage Output Low Voltage Output Low Current Output Leakage Current Pad Capacitance Min VCCP - 5% 0 16 -- 1.80 Typ VCCP -- -- -- 2.30 Max VCCP + 5% 0.20 50 200 2.75 Unit V V mA A pF 2 4 5 Notes1 3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2 V. 3. VOH is determined by value of the external pull-up resistor to VCCP. Refer to the appropriate platform design guide for details. 4. For Vin between 0 V and VOH. 5. Cpad includes die capacitance only. No package parasitics are included.
36
Datasheet
Package Mechanical Specifications and Pin Information
4
Package Mechanical Specifications and Pin Information
Package Mechanical Specifications
The processor is available in 6-MB and 3-MB, 478-pin Micro-FCPGA packages as well as 6-MB and 3-MB, 479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 7 through Figure 10. The mechanical package pressure specifications are in a direction normal to the surface of the processor. This requirement is to protect the processor die from fracture risk due to uneven die pressure distribution under tilt, stack-up tolerances and other similar conditions. These specifications assume that a mechanical attach is designed specifically to load one type of processor. Intel also specifies that 15-lbf load limit should not be exceeded on any of Intel's BGA packages so as to not impact solder joint reliability after reflow. This load limit ensures that impact to the package solder joints due to transient bend, shock, or tensile loading is minimized. The 15-lbf metric should be used in parallel with the 689 kPa (100 psi) pressure limit as long as neither limits are exceeded. In some cases, designing to 15-lbf will exceed the pressure specification of 689 kPa (100 psi) and therefore should be reduced to ensure both limits are maintained. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for the thermal or mechanical solution. Refer to the Santa Rosa Platform Mechanical Design Guide for details.
4.1
Caution:
The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive so care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors and possibly damage the device or render it inactive.
Datasheet
37
h
38
Figure 7.
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
B1 H1 G1
B
479 PINS
C2 G2
B2
H2 J2
C1 A
SIDE VIEW
J1
B1
BOTTOM VIEW
SYMBOL B2 C1 C2 MILLIMETERS
MIN MAX
TOP VIEW
Underfill Die
COMMENTS 34.95 34.95 8.7 12.4 0.88 G1 F2 F3 1.862 G2 2.102 31.75 BASIC 31.75 BASIC 15.875 BASIC 35.05 35.05
Package Substrate
0.37 MAX
F2 F3
H1 H2 J1
15.875 BASIC
2.030.08
o0.356 M o0.254 M
J2 1.27 BASIC 1.27 BASIC
CAB C
0.65 MAX
A
FRONT VIEW
0.65 MAX P
C
P W
0.255 6g Keying Pins
0.355 A1, A2
DETAIL SCALE 20
A
6-MB and 3-MB on 6-MB Die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)
Package Mechanical Specifications and Pin Information
B6667-01 D76563
Datasheet
Datasheet
o0.3050.25 o0.406 M C A B o0.254 M C
4x 7.00
6.985 13.97 1.625 1.625
Figure 8.
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
4x 7.00
Package Mechanical Specifications and Pin Information
13.97
6.985
4x 5.00
EDGE KEEP OUT ZONE 4X
TOP VIEW
CORNER KEEP OUT ZONE 4X
SIDE VIEW
1.5 MAX ALLOWABLE COMPONENT HEIGHT
BOTTOM VIEW
6-MB and 3-MB on 6-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)
B6668-01 D76563
39
40
Figure 9.
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
B
B1
479 Balls
B
H1
G1
C2
B2
G2
H2
J2
C1 A
TOP VIEW
SYMBOL 34.95 34.95
MIN
SIDE VIEW
MILLIMETERS 35.05 35.05
MAX
J1
BOTTOM VIEW
Underfill Package Substrate Die
COMMENTS
F2
A
FRONT VIEW
M
F3
C N
0.203
DETAIL
o0.203 L o0.071 L
CAB
B1 B2 C1 C2 F2 F3 G1 G2 H1 H2 J1 J2
SCALE 20
A
6-MB and 3-MB on 6-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)
Package Mechanical Specifications and Pin Information
DETAIL
Datasheet
SCALE 50
B
M N W
8.7 12.4 0.88 1.937 2.207 31.75 BASIC 31.75 BASIC 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.61 0.69 0.6 0.8 6g
B6643-02 D76560_1_6M_BGA
Datasheet
13.97 4x 7.00 6.985 1.625 4x 7.00 1.625 13.97 6.985 4x 5.00
CORNER KEEP OUT ZONE 4X
Figure 10.
Package Mechanical Specifications and Pin Information
G CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE ENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR SENT OF INTEL CORPORATION.
EDGE KEEP OUT ZONE 4X
SIDE VIEW
0.55 MAX ALLOWABLE COMPONENT HEIGHT
TOP VIEW
BOTTOM VIEW
6-MB and 3-MB on 6-MB die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)
B664 D76560_2_6M
41
Package Mechanical Specifications and Pin Information
Figure 11.
3-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)
42
Datasheet
Package Mechanical Specifications and Pin Information
Figure 12.
3-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)
Datasheet
43
44
Figure 13.
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
B
B1
479 Balls
SEE DETAIL B
H1
G1
C2
B2
G2
H2 J2
TOP VIEW
SYMBOL B1 B2 8.7 9.4 0.88 1.937 2.207 34.95 34.95 35.05 35.05
MIN MAX
C1
A
SIDE VIEW
J1
BOTTOM VIEW
MILLIMETERS COMMENTS
Package Substrate
Underfill
Die
F2
FRONT VIEW
F2 F3
SEE DETAIL
G1
A
G2 H1 H2 J1 J2 M N
DETAIL SCALE 50
C1 C2
F3
C N
DETAIL SCALE 20
3-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)
M
31.75 BASIC 31.75 BASIC 15.875 BASIC 15.875 BASIC 1.27 BASIC 1.27 BASIC 0.61 0.6 0.69 0.8
A
o0.203 L o0.071 L
CAB
0.203
Package Mechanical Specifications and Pin Information
Datasheet
B
W
6g
B6645-02 D93702_1_3M_BGA
Datasheet
13.97 4x 7.00 6.985 1.625 4x 7.00 1.625 13.97 6.985 4x 5.00 CORNER KEEP OUT ZONE 4X
Figure 14.
Package Mechanical Specifications and Pin Information
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN
EDGE KEEP OUT ZONE 4X
SIDE VIEW
0.55 MAX ALLOWABLE COMPONENT HEIGHT
3-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)
TOP VIEW
BOTTOM VIEW
B6646-02 D93702_2_3M_BGA
45
Package Mechanical Specifications and Pin Information
4.2
Processor Pinout and Pin List
Figure 15 and Figure 16 show the processor pinout as viewed from the top of the package. Table 12 provides the pin list, arranged numerically by pin number.
Figure 15.
1 A1 B1 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF RESET# VSS DBSY# BR0# VSS ADS# A[9]# VSS REQ[4]# ADSTB[0]# VSS A[15]# A[16]# VSS A[23]# ADSTB[1]# VSS COMP[3] COMP[2] VSS PREQ# BPM[2]# VSS TEST5 1
Processor Pinout (Top Package View, Left Side)
2 VSS RSVD VSS RSVD BNR# VSS TRDY# REQ[1]# VSS REQ[2]# A[13]# VSS A[8]# A[12]# VSS RSVD A[30]# VSS A[27]# A[17]# VSS A[34]# PRDY# VSS VID[6] VSS 2 3 SMI# INIT# TEST7 RSVD VSS RS[0]# RS[2]# VSS REQ[3]# REQ[0]# VSS A[7]# A[10]# VSS A[19]# A[26]# VSS RSVD A[32]# VSS A[35]# TDO VSS BPM[1]# VID[4] VID[5] 3 4 VSS LINT1 IGNNE# VSS HITM# RS[1]# VSS LOCK# A[3]# VSS A[5]# RSVD VSS A[14]# A[24]# VSS A[21]# A[31]# VSS A[29]# A[33]# VSS BPM[3]# BPM[0]# VSS VID[3] 4 5 FERR# DPSLP# VSS STPCLK# DPRSTP# VSS BPRI# DEFER# VSS A[6]# A[4]# VSS RSVD A[11]# VSS A[25]# A[18]# VSS A[28]# A[22]# VSS TMS TCK VSS VID[2] VID[1] 5 6 A20M# VSS LINT0 PWRGO OD VSS RSVD HIT# VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP A[20]# VSS TDI TRST# VSS VID[0] PSI# VSS 6 VCC VCC VCC VCC VSS SENSE VCC SENSE 7 VSS VSS VSS VSS VSS VSS 8 VCC VCC VCC VCC VCC VCC 9 VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS VSS 11 VCC VCC VCC VCC VCC VCC 12 VCC VSS VCC VSS VCC VSS 13 7 VCC VCC THERM TRIP# SLP# VCC VCC 8 VSS VSS VSS VSS VSS VSS 9 VCC VCC VCC VCC VCC VCC 10 VCC VCC VCC VCC VCC VCC 11 VSS VSS VSS VSS VSS VSS 12 VCC VCC VCC VCC VCC VCC 13 VCC VSS VCC VSS VCC VSS A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
NOTES: 1. Keying option for FCPGA, A1 and B1 are depopulated. 2. Keying option for FCBGA, A1 is depopulated and B1 is VSS.
46
Datasheet
Package Mechanical Specifications and Pin Information
Figure 16.
14 A B C D E F G H J K L M N P R T U V W Y AA AB AC A D AE AF VSS VCC VSS VCC VSS VCC 14 VCC VCC VCC VCC VCC VCC 15 VSS VCC VSS VCC VSS VCC 15 VCC VCC VCC VCC VCC VCC
Processor Pinout (Top Package View, Right Side)
16 VSS VSS VSS VSS VSS VSS 17 VCC VCC VCC VCC VCC VCC 18 VCC VCC VCC VCC VCC VCC 19 VSS VSS VSS VSS VSS VSS 20 VCC VCC DBR# IERR# VCC VCC 21 BCLK[1] VSS BSEL[2] PROCHOT # VSS DRDY# VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VCCP VCCP VSS VSS VSS VSS VSS VSS VSS 16 VCC VCC VCC VCC VCC VCC 17 VCC VCC VCC VCC VCC VCC 18 VSS VSS VSS VSS VSS VSS 19 VCC VCC DINV[3]# D[54]# VCC VCC 20 D[50]# D[52]# VSS D[59]# D[58]# VSS 21 22 BCLK[0] BSEL[0] VSS RSVD D[0]# VSS D[3]# D[12]# VSS D[14]# D[22]# VSS D[16]# D[26]# VSS D[37]# DINV[2]# VSS D[41]# D[32]# VSS D[51]# D[60]# VSS D[55]# D[62]# 22 23 VSS BSEL[1] TEST1 VSS D[7]# D[4]# VSS D[15]# D[11]# VSS D[20]# D[23]# VSS D[25]# D[19]# VSS D[39]# D[36]# VSS D[42]# D[45]# VSS D[63]# D[61]# VSS D[56]# 23 24 THRMDA VSS TEST3 DPWR# VSS D[1]# D[9]# VSS D[10]# D[8]# VSS D[21]# DINV[1]# VSS D[28]# D[27]# VSS D[34]# D[43]# VSS D[46]# D[33]# VSS D[49]# D[48]# DSTBP[3]# 24 25 VSS THRMDC VSS TEST2 D[6]# VSS D[5]# DINV[0]# VSS D[17]# D[29]# VSS D[31]# D[24]# VSS D[30]# D[38]# VSS D[44]# D[40]# VSS D[47]# D[57]# VSS DSTBN[3]# VSS 25 26 TEST6 VCCA VCCA VSS D[2]# D[13]# VSS DSTBP[ 0]# DSTBN[ 0]# VSS DSTBN[ 1]# DSTBP[ 1]# VSS D[18]# COMP[0 ] VSS COMP[1 ] D[35]# VSS DSTBN[ 2]# DSTBP[ 2]# VSS D[53]# GTLREF VSS TEST4 26 A B C D E F G H J K L M N P R T U V W Y A A A B AC A D AE AF
Datasheet
47
Package Mechanical Specifications and Pin Information
Table 12. Table 12.
Pin Name
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]#
Pin Listing by Pin Name
Pin #
W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 A6 H1 M1 V1 A22 A21 E2 AD4 AD3 AD1 AC4 G5 F1 B22 B23 C21 R26 U26 AA1
Pin Listing by Pin Name
Pin #
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3
Pin Name
A[27]#
Signal Buffer Type
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch
Signal Buffer Type
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Source Synch Source Synch Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock CMOS CMOS CMOS Power/Other Power/Other Power/Other
Direction
Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input Input Input/ Output Input/ Output Output Output Input/ Output Input Input/ Output Output Output Output Input/ Output Input/ Output Input/ Output
Direction
Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output
A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# A20M# ADS# ADSTB[0]# ADSTB[1]# BCLK[0] BCLK[1] BNR# BPM[0]# BPM[1]# BPM[2]# BPM[3]# BPRI# BR0# BSEL[0] BSEL[1] BSEL[2] COMP[0] COMP[1] COMP[2]
Datasheet
48
Package Mechanical Specifications and Pin Information
Table 12.
Pin Name
COMP[3] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]#
Pin Listing by Pin Name
Pin #
Y1 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 N22 K25 P26 R23 L23 M24 L22 M23
Table 12.
Pin Name
D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]#
Pin Listing by Pin Name
Pin #
P25 P23 P22 T24 R24 L25 T25 N25 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 AE24
Signal Buffer Type
Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch
Direction
Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output
Signal Buffer Type
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch
Direction
Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output
Datasheet
49
Package Mechanical Specifications and Pin Information
Table 12.
Pin Name
D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DBR# DBSY# DEFER# DINV[0]# DINV[1]# DINV[2]# DINV[3]# DPRSTP# DPSLP# DPWR# DRDY# DSTBN[0]#
Pin Listing by Pin Name
Pin #
AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 C20 E1 H5 H25 N24 U22 AC20 E5 B5 D24 F21 J26
Table 12.
Pin Name
DSTBN[1]# DSTBN[2]# DSTBN[3]# DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR# GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# PRDY# PREQ# PROCHOT# PSI# PWRGOOD REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# RESET# RS[0]# RS[1]# RS[2]#
Pin Listing by Pin Name
Pin #
L26 Y26 AE25 H26 M26 AA26 AF24 A5 AD26 G6 E4 D20 C4 B3 C6 B4 H4 AC2 AC1 D21 AE6 D6 K3 H2 K2 J3 L1 C1 F3 F4 G3
Signal Buffer Type
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch CMOS Common Clock Common Clock Source Synch Source Synch Source Synch Source Synch CMOS CMOS Common Clock Common Clock Source Synch
Direction
Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input/ Output Input/ Output Input/ Output
Signal Buffer Type
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Open Drain Power/Other Common Clock Common Clock Open Drain CMOS CMOS CMOS CMOS Common Clock Common Clock Common Clock Open Drain CMOS CMOS Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Common Clock Common Clock Common Clock
Direction
Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Output Input Input/ Output Input/ Output Output Input Input Input Input Input/ Output Output Input Input/ Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input Input
50
Datasheet
Package Mechanical Specifications and Pin Information
Table 12.
Pin Name
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SLP# SMI# STPCLK# TCK TDI TDO TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 THERMTRIP# THRMDA THRMDC TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Pin Listing by Pin Name
Pin #
B2 D2 D3 D22 F6 M4 N5 T2 V3 D7 A3 D5 AC5 AA6 AB3 C23 D25 C24 AF26 AF1 A26 C3 C7 A24 B25 AB5 G2 AB6 A7 A9 A10 A12 A13 A15 A17 A18 A20 AA7 AA9 AA10
Table 12.
Pin Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC
Pin Listing by Pin Name
Pin #
AA12 AA13 AA15 AA17 AA18 AA20 AB7 AB9 AB10 AB12 AB14 AB15 AB17 AB18 AB20 AC7 AC9 AC10 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9
Signal Buffer Type
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CMOS CMOS CMOS CMOS CMOS Open Drain Test Test Test Test Test Test Test Open Drain Power/Other Power/Other CMOS Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Input Input Input Input Input Output
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Output
VCC VCC VCC
Input Input Input
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Datasheet
51
Package Mechanical Specifications and Pin Information
Table 12.
Pin Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Pin Listing by Pin Name
Pin #
AF10 AF12 AF14 AF15 AF17 AF18 AF20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7
Table 12.
Pin Name
VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCSENSE VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VSS VSS VSS VSS VSS VSS
Pin Listing by Pin Name
Pin #
F9 F10 F12 F14 F15 F17 F18 F20 B26 C26 G21 J6 J21 K6 K21 M6 M21 N6 N21 R6 R21 T6 T21 V6 V21 W21 AF7 AD6 AF5 AE5 AF4 AE3 AF3 AE2 A2 A4 A8 A11 A14 A16
Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Output Output Output Output Output Output Output
52
Datasheet
Package Mechanical Specifications and Pin Information
Table 12.
Pin Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Pin Listing by Pin Name
Pin #
A19 A23 A25 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1
Table 12.
Pin Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Pin Listing by Pin Name
Pin #
AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF25 B6 B8 B11 B13 B16 B19 B21 B24 C2 C5 C8 C11 C14 C16 C19 C22 C25 D1 D4 D8 D11 D13 D16
Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Datasheet
53
Package Mechanical Specifications and Pin Information
Table 12.
Pin Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Pin Listing by Pin Name
Pin #
D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F2 F5 F8 F11 F13 F16 F19 F22 F25 G1 G4 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21
Table 12.
Pin Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSENSE
Pin Listing by Pin Name
Pin #
L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AE7
Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Output
54
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Listing by Pin Number
Signal Buffer Type keying option Power/Other CMOS Power/Other Open Drain CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Bus Clock Bus Clock Power/Other Power/Other Power/Other Test Power/Other Power/Other Source Synch Source Synch Power/Other CMOS Power/Other Power/other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input/ Output Input/ Output Input/ Output Input Input Output Input Input Direction
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Open Drain Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input Input Input/ Output Output Input/ Output Input/ Output Input/ Output Input/ Output Direction
Pin # Pin Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 Depopulated VSS SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THRMDA VSS TEST6 COMP[2] VSS A[35]# A[33]# VSS TDI VCC VSS VCC VCC VSS VCC VCC VSS
Pin # Pin Name AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 VCC VSS VCC VCC VSS VCC D[50]# VSS D[45]# D[46]# VSS DSTBP[2]# VSS A[34]# TDO VSS TMS TRST# VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC D[52]# D[51]# VSS D[33]# D[47]#
Datasheet
55
Package Mechanical Specifications and Pin Information
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Common Clock Input Common Clock Output Power/Other Input/ Common Clock Output CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Direction
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other CMOS CMOS Power/Other CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Output Output Output Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output Direction
Pin # Pin Name AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 VSS PREQ# PRDY# VSS BPM[3]# TCK VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DINV[3]# VSS D[60]# D[63]# VSS D[57]# D[53]# BPM[2]# VSS BPM[1]# BPM[0]# VSS VID[0] VCC VSS VCC VCC VSS
Pin # Pin Name AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 VCC VSS VCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS D[61]# D[49]# VSS GTLREF VSS VID[6] VID[4] VSS VID[2] PSI# VSSSENSE VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC D[58]# D[55]# VSS
Common Clock Output Power/Other Common Clock Output Common Clock Power/Other CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Output Input/ Output
AE20 AE21 AE22 AE23
56
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Source Synch Source Synch Power/Other Test Power/Other CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Power/Other Test Keying option Reserved CMOS CMOS CMOS Power/Other Power/Other Power/Other Input Input Input Input/ Output Input/ Output Input/ Output Output Output Output Direction Input/ Output Input/ Output
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Power/Other Power/Other Common Clock Input Power/Other TEST CMOS Power/Other CMOS Open Drain Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Test Test Output Output Input Output Input Output Output Direction
Pin # Pin Name AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 D[48]# DSTBN[3]# VSS TEST5 VSS VID[5] VID[3] VID[1] VSS VCCSENSE VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]# DSTBP[3]# VSS TEST4 Depopulated for FCPGA VSS for FCBGA RSVD INIT# LINT1 DPSLP# VSS VCC VSS
Pin # Pin Name B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS THRMDC VCCA RESET# VSS TEST7 IGNNE# VSS LINT0 THERMTRIP# VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DBR# BSEL[2] VSS TEST1 TEST3
Datasheet
57
Package Mechanical Specifications and Pin Information
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Power/Other Power/Other Reserved Reserved Power/Other CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain Open Drain Reserved Power/Other Common Clock Test Power/Other Input/ Common Clock Output Input/ Common Clock Output Power/Other Common Clock CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/ Output Input Input/ Output Output Input/ Output Input Input Input Direction
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Common Clock Power/Other Common Clock Input Common Clock Input Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Power/Other Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction
Pin # Pin Name C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 VSS VCCA VSS RSVD RSVD VSS STPCLK# PWRGOOD SLP# VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS IERR# PROCHOT# RSVD VSS DPWR# TEST2 VSS DBSY# BNR# VSS HITM# DPRSTP# VSS VCC VSS VCC VCC VSS
Pin # Pin Name E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS D[6]# D[2]# BR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]#
58
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Source Synch Power/Other Source Synch Power/Other Common Clock Input Common Clock Input Power/Other Common Clock Input Common Clock Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Common Clock Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction
Pin # Pin Name F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 D[1]# VSS D[13]# VSS TRDY# RS[2]# VSS BPRI# HIT# VCCP D[3]# VSS D[9]# D[5]# VSS ADS# REQ[1]# VSS LOCK# DEFER# VSS VSS D[12]# D[15]# VSS DINV[0]# DSTBP[0]# A[9]# VSS REQ[3]# A[3]# VSS VCCP
Pin # Pin Name J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 K23 K24 K25 K26 L1 L2 L3 VCCP VSS D[11]# D[10]# VSS DSTBN[0]# VSS REQ[2]# REQ[0]# VSS A[6]# VCCP VCCP D[14]# VSS D[8]# D[17]# VSS REQ[4]# A[13]# VSS A[5]# A[4]# VSS VSS D[22]# D[20]# VSS D[29]# DSTBN[1]# ADSTB[0]#
Common Clock Input Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output
L4 L5 L6 L21 L22 L23 L24 L25 L26 M1
59
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Source Synch Reserved Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Reserved Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Reserved Source Synch Power/Other Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output Input/ Output Input/ Output
Pin # Pin Name M2 M3 M4 M5 M6 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P21 P22 P23 P24 VSS A[7]# RSVD VSS VCCP VCCP VSS D[23]# D[21]# VSS DSTBP[1]# VSS A[8]# A[10]# VSS RSVD VCCP VCCP D[16]# VSS DINV[1]# D[31]# VSS A[15]# A[12]# VSS A[14]# A[11]# VSS VSS D[26]# D[25]# VSS
Pin # Pin Name P25 P26 R1 R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 D[24]# D[18]# A[16]# VSS A[19]# A[24]# VSS VCCP VCCP VSS D[19]# D[28]# VSS COMP[0] VSS RSVD A[26]# VSS A[25]# VCCP VCCP D[37]# VSS D[27]# D[30]# VSS A[23]# A[30]# VSS A[21]# A[18]# VSS
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Package Mechanical Specifications and Pin Information
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Power/Other Reserved Source Synch Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction
Table 13.
Pin Listing by Pin Number
Signal Buffer Type Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Direction Input/ Output
Pin # Pin Name U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 VSS DINV[2]# D[39]# VSS D[38]# COMP[1] ADSTB[1]# VSS RSVD A[31]# VSS VCCP VCCP VSS D[36]# D[34]# VSS D[35]# VSS A[27]# A[32]# VSS A[28]# A[20]# VCCP D[41]# VSS D[43]# D[44]# VSS COMP[3]
Pin # Pin Name Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26 A[17]# VSS A[29]# A[22]# VSS VSS D[32]# D[42]# VSS D[40]# DSTBN[2]#
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Table 14.
Signal Description (Sheet 1 of 8)
Name Type Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps, which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address Bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the TRDY# assertion of the corresponding input/ output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB[0]# ADSTB[1]#
A[35:3]#
Input/ Output
A20M#
Input
ADS#
Input/ Output
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
BNR#
Input/ Output
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all processor FSB agents.This includes debug or performance monitoring tools. Refer to the appropriate eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms for detailed information.
BPM[2:1]# BPM[3,0]#
Output Input/ Output
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Table 14.
Signal Description (Sheet 2 of 8)
Name Type Description BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done between the processor (Symmetric Agent) and GMCH (High Priority Agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the appropriate platform design guide for more details on implementation. D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV# . D[63:0]# Input/ Output Quad-Pumped Signal Groups Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3
BPRI#
Input
BR0#
Input/ Output
BSEL[2:0]
Output
COMP[3:0]
Analog
Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a noconnect in the system. DBR# is not a processor signal.
DBR#
Output
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Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 3 of 8)
Name Type Input/ Output Description DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins of both FSB agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment to Data Bus DINV[3:0]# Input/ Output Bus Signal DINV[3]# DINV[2]# DINV[1]# DINV[0]# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]#
DBSY#
DEFER#
Input
DPRSTP#
Input
DPRSTP#, when asserted on the platform, causes the processor to transition from the Deep Sleep State to the Deeper Sleep state or C6 state. To return to the Deep Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the ICH8M chipset. DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. To return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the ICH8M chipset. DPWR# is a control signal used by the chipset to reduce power on the processor data bus input buffers. The processor drives this pin during dynamic FSB frequency switching. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]#
DPSLP#
Input
DPWR#
Input/ Output
DRDY#
Input/ Output
DSTBN[3:0]#
Input/ Output
D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]#
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Table 14.
Signal Description (Sheet 4 of 8)
Name Type Description Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# Input/ Output D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]#
FERR#/PBE#
Output
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volumes 3A and 3B of the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals and the CPUID Instruction Application Note. Refer to the appropriate platform design guide for termination requirements.
GTLREF HIT# HITM#
Input Input/ Output Input/ Output
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a Logical 0 or Logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall that can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by the processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IERR#
Output
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Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 5 of 8)
Name Type Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a non-control floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in Control Register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the TRDY# assertion of the corresponding input/ output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the TRDY# assertion of the corresponding input/output write bus transaction. INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active-to-inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software-configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Probe Request signal used by debug tools to request debug operation of the processor.
IGNNE#
Input
INIT#
Input
LINT[1:0]
Input
LOCK#
Input/ Output
PRDY# PREQ#
Output Input
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Table 14.
Signal Description (Sheet 6 of 8)
Name Type Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#. By default PROCHOT# is configured as an output. The processor must be enabled via the BIOS for PROCHOT# to be configured as bidirectional. PSI# Output Processor Power Status Indicator signal. This signal is asserted when the processor is both in the normal state (HFM to LFM) and in lower power states (Deep Sleep and Deeper Sleep). PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. `Clean' implies that the signal remains low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Input/ Output REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use.
PROCHOT#
Input/ Output
PWRGOOD
Input
REQ[4:0]#
RESET#
Input
RS[2:0]#
Input Reserved/ No Connect
RSVD
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Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 7 of 8)
Name Type Description SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to StopGrant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enters System Management Mode (SMM). An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler. If an SMI# is asserted during the deassertion of RESET#, then the processor will tristate its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low-power stop-grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.
SLP#
Input
SMI#
Input
STPCLK#
Input
TCK TDI
Input Input
TDO TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 THRMDA THRMDC
Output
Input
TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, and TEST7 have termination requirements.
Other Other
Thermal Diode Anode. Thermal Diode Cathode. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.
THERMTRIP#
Output
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Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 8 of 8)
Name TMS Type Input Description TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Processor core power supply. Processor core ground node. VCCA provides isolated power for the internal processor core PLLs. Processor I/O Power Supply. VCC_SENSE together with VSS_SENSE are voltage feedback signals to Intel(R) MVP6 that control the 2.1-m loadline at the processor die. It should be used to sense voltage near the silicon with little noise. Refer to the platform design guide for termination and routing recommendations. VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the processor. The voltage supply for these pins must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSS_SENSE together with VCC_SENSE are voltage feedback signals to Intel MVP6 that control the 2.1-m loadline at the processor die. It should be used to sense ground near the silicon with little noise. Refer to the platform design guide for termination and routing recommendations.
TRDY# TRST# VCC VSS VCCA VCCP
Input Input Input Input Input Input
VCC_SENSE
Output
VID[6:0]
Output
VSS_SENSE
Output
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Thermal Specifications
5
Thermal Specifications
Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system-level thermal management features. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so the processor remains within the minimum and maximum junction temperature (TJ) specifications at the corresponding thermal design power (TDP) value listed in Table 15. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods.
Table 15.
Power Specifications for the Extreme Edition Processor
Symbol Processor Number X9000 TDP Symbol PAH, PSGNT at VCCHFM at VCCSLFM Sleep Power PSLP at VCCHFM at VCCSLFM Deep Sleep Power PDSLP PDPRSLP PDC4 PC6 TJ at VCCHFM at VCCSLFM Deeper Sleep Power Intel(R) Enhanced Deeper Sleep State Power Deep Power-Down Technology Power Junction Temperature -- -- -- 0 -- -- -- -- -- -- 7.5 4.2 1.9 1.7 1.3 105 W W W C 2,8 2,8 2, 8 3, 4 W 2, 5, 8 -- -- 16.1 7.1 W 2, 5, 7 Core Frequency & Voltage 2.8 GHz & VCCHFM 1.2 GHz & VCCLFM 0.8 GHz & VCCSLFM Parameter Auto Halt, Stop Grant Power -- -- 17.1 7.4 W 2, 5, 7 Min Thermal Design Power 44 29 22 Typ Max Unit W Unit Notes 1, 4, 5, 6 Notes
NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor's automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is less than TDP in HFM. 6. At Tj of 105oC 7. At Tj of 50oC 8. At Tj of 35oC
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Thermal Specifications
Table 16.
Power Specifications for Dual-Core Standard Voltage Processors
Symbol Processor Number T9500 T9300 T8300 T8100 Core Frequency & Voltage 2.6 GHz & VCCHFM 2.5 GHz & VCCHFM 2.4 GHz & VCCHFM 2.1 GHz & VCCHFM 1.2 GHz & VCCLFM 0.8 GHz & VCCLFM Symbol PAH, PSGNT at VCCHFM at VCCSLFM Sleep Power PSLP at VCCHFM at VCCSLFM Deep Sleep Power PDSLP PDPRSLP PDC4 PC6 TJ at VCCHFM at VCCSLFM Deeper Sleep Power Intel(R) Enhanced Deeper Sleep State Power Deep Power-Down Technology Power Junction Temperature -- -- -- 0 -- -- -- -- -- -- 5.5 2.2 1.7 1.3 0.3 105 W W W C 2, 8 2, 8 2, 8 3, 4 W 2, 5, 8 -- -- 11.8 4.8 W 2, 5, 7 Parameter Auto Halt, Stop Grant Power -- -- 12.5 5.0 W 2, 5, 7 Min Thermal Design Power 35 35 35 35 22 12 Typ Max Unit W 1, 4, 5, 6 Unit Notes
TDP
NOTES: 1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor's automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details. 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is lesser than TDP in HFM. 6. At Tj of 105oC 7. At Tj of 50oC 8. At Tj of 35oC
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Thermal Specifications
5.1
Thermal Features
The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.
Caution:
Operating the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. The processor incorporates three methods of monitoring die temperature: * Thermal diode * Intel Thermal Monitor * Digital thermal sensor
Note:
The Intel Thermal Monitor (detailed in Section 5.1.2) must be used to determine when the maximum specified processor junction temperature has been reached.
5.1.1
Thermal Diode
Intel's processors utilize an SMBus thermal sensor to read back the voltage/current characteristics of a substrate PNP transistor. Since these characteristics are a function of temperature, in principle one can use these parameters to calculate silicon temperature values. For older silicon process technologies it was possible to simplify the voltage/current and temperature relationships by treating the substrate transistor as though it were a simple diffusion diode. In this case, the assumption is that the beta of the transistor does not impact the calculated temperature values. The resultant diode model essentially predicts a quasi linear relationship between the base/emitter voltage differential of the PNP transistor and the applied temperature (one of the proportionality constants in this relationship is processor specific, and is known as the diode ideality factor). Realization of this relationship is accomplished with the SMBus thermal sensor that is connected to the transistor. This processor, however, is built on Intel's advanced 45-nm processor technology. Due to this new, highly-advanced processor technology, it is no longer possible to model the substrate transistor as a simple diode. To accurately calculate silicon temperature one must use a full bi-polar junction transistor-type model. In this model, the voltage/ current and temperature characteristics include an additional process dependant parameter which is known as the transistor "beta". System designers should be aware that the current thermal sensors on Santa Rosa platforms may not be configured to account for "beta" and should work with their SMB thermal sensor vendors to ensure they have a part capable of reading the thermal diode in BJT model. Offset between the thermal diode-based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor's Automatic mode activation of the thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor model-specific register (MSR). Table 17 to Table 18 provide the diode interface and transistor model specifications.
Table 17.
Thermal Diode Interface
Signal Name THERMDA THERMDC Pin/Ball Number A24 B25 Signal Description Thermal diode anode Thermal diode cathode
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Thermal Specifications
Table 18.
Thermal Diode Parameters using Transistor Model
Symbol IFW IE nQ Beta RT Series Resistance Parameter Forward Bias Current Emitter Current Transistor Ideality Min 5 5 0.997 0.1 3.0 Typ -- -- 1.001 0.4 4.5 Max 200 200 1.008 0.5 7.0 Unit A A
1 1 2, 3, 4 2, 3 2
Notes
NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized across a temperature range of 50-105C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * (e qVBE/nQkT -1) where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin).
5.1.2
Intel(R) Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the TCC (thermal control circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power-intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence. There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2). These modes are selected by writing values to the MSRs of the processor. After automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. When TM1 is enabled and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed-dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid
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active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. When TM2 is enabled and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. The processor also supports Enhanced Multi Threaded Thermal Monitoring (EMTTM). EMTTM is a processor feature that enhances TM2 with a processor throttling algorithm known as Adaptive TM2. Adaptive TM2 transitions to intermediate operating points, rather than directly to the LFM, once the processor has reached its thermal limit and subsequently searches for the highest possible operating point. Please ensure this feature is enabled and supported in the BIOS. Also with EMTTM enabled, the OS can request the processor to throttling to any point between Intel Dynamic Acceleration Technology frequency and SuperLFM frequency as long as these features are enabled in the BIOS and supported by the processor. The Intel Thermal Monitor automatic mode and Enhanced Multi Threaded Thermal Monitoring must be enabled through BIOS for the processor to be operating within specifications. Intel recommends TM1 and TM2 be enabled on the processors. TM1, TM2 and EMTTM features are collectively referred to as adaptive thermal monitoring features. TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 will take precedence over TM1. However, if Force TM1 over TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below the maximum operating temperature, then TM1 will also activate to help cool down the processor. If a processor load-based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when a TM2 period is active, there are two possible results: 1. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is higher than the TM2 transition-based target frequency, the processor load-based transition will be deferred until the TM2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the TM2 transition-based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated via on-demand mode. If Bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via Bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on/50% off; however, in on-demand mode the duty cycle can be programmed from 12.5% on/87.5% off to 87.5% on/12.5% off, in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active.
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Thermal Specifications
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low-power states, hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above lowpower states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor junction temperature drops below the thermal trip point. If thermal monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.
5.1.3
Digital Thermal Sensor
The processor also contains an on-die digital thermal sensor (DTS) that can be read via an MSR (no I/O interface). Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the thermal monitor. The DTS is only valid while the processor is in the normal operating state (the normal package level low-power state). Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (TJ,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Catastrophic temperature conditions are detectable via an out of specification status bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not ensured once the activation of the out of specification status bit is set. The DTS-relative temperature readout corresponds to the thermal monitor (TM1/TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached, the TM1 or TM2 hardware thermal control mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach, and software application. The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications.
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Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel(R) 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.
5.2
Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shutdown before the THERMTRIP# is activated. If the processor's TM1 or TM2 are triggered and the temperature remains high, an "Out Of Spec" status and sticky bit are latched in the status MSR register, and it generates a thermal interrupt.
5.3
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If TM1 or TM2 is enabled, then the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. Only a single PROCHOT# pin exists at a package level of the processor. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only TM1 is enabled, PROCHOT# will be asserted regardless of which core is above TCC temperature trip point, and both cores will have their core clocks modulated. If TM2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed TM2 performance state. It is important to note that Intel recommends both TM1 and TM2 to be enabled. When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores, then both processor cores will have their core clocks modulated. If TM2 is enabled on both cores, then both processor cores will enter the lowest programmed TM2 performance state. It should be noted that force TM1 on TM2, enabled via BIOS, does not have any effect on external PROCHOT#. If PROCHOT# is driven by an external agent when TM1, TM2, and force TM1 on TM2 are all enabled, then the processor will still apply only TM2. PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.
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